Simple FPGA 2D graphic accelerator. Design allows relatively slow microcontrollers to display images or short animations on LCD up to 1920x1080px via HDMI.
After writing bitmaps to SDRAM, controlling images being displayed is effortless.
How it works:
Memory is allocated as 4 banks 8192 rows each. FPGA allows to write to any address within SDRAM. Due to strictly software realization of transfer in STM32 it takes a lot of time to load full size of SDRAM.
After loading all necessary bitmaps, STM32 writes up to 32 images coordinates(x, y, width, height, SDRAM address, ...).
FPGA immediatelly starts to render dispayed image.
FPGA renders images into ping-pong buffer located in embedded RAM, that dramatically reduce memory bandwidth requirements.
At this stage FPGA performs alpha color masking, which naturally makes non rectangular shapes.
Images are drawn in order, so overlapping effect is easily achieved.
- DDR SDRAM bandwidth limits amount of loaded pixels to approximately 3200px per line.
- Also width of each image cannot exceed 500px due to SDRAM row size.
- Big disadvantage is lack of vertical synchronization, which sometimes leads to tear effect.