NOTE: this project was imported from Altium Designer

ToDo: assembly precision resistors, final performance measurements, finish control software, design and build enclosure

AWG_2xAD9102

Dual channel, AD9102 (14-Bit, 180 MSPS DDS DAC) based "arbitrary" waveform generator [sine (phase-shifted, delayed, amplitude modulated), sawtooth, pseudorandom, DC or arbitrary pattern stored in SRAM 4096 x 12bit]. Outputs are differential, buffered, impedance matched, with independently controllable amplitude and DC offset.

DC offset of the output buffers as well as DDS output swing is controllable via quad 10-bit DAC related to common voltage reference.

Source of DDS DACs reference clock (10*2^24 or  180 MHz) is TI CDCI6214, locked on onboard TCXO or external source.

Digital control bus is connected through digital isolators.

Output voltage @ 50 Ω load: max. 1 Vpp

HD2/HD3: TBD

SNR: TBD

AWG_2xAD9102-PWR AMP

Each channel comprises of dual parallel THS3091 or enhanced THS3491 CFA "power" amplifiers.

One unique feature is a relay to switch the input of the amplifier between single-ended or differential drive. This itself prevents saturation of the amplifiers output, the DC offset in differential drive is substracted.

Output voltage @ 50 Ω load: max. 5 Vpp (single-ended drive), 10 Vpp (diff. drive)

HD2/HD3: TBD

SNR: TBD